plat/css: allow platforms to define the system power domain level
authorChandni Cherukuri <[email protected]>
Tue, 16 Oct 2018 09:49:54 +0000 (15:19 +0530)
committerChandni Cherukuri <[email protected]>
Tue, 27 Nov 2018 05:02:55 +0000 (10:32 +0530)
The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain
level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the
system power domain level can be different for CSS platforms that
use multi-threaded CPUs.

So, in preparation towards adding support for platforms that use
multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL
such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the
CSS platform.

Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85
Signed-off-by: Chandni Cherukuri <[email protected]>
include/plat/arm/css/common/css_pm.h
plat/arm/board/juno/include/platform_def.h
plat/arm/board/n1sdp/include/platform_def.h
plat/arm/board/sgi575/include/platform_def.h
plat/arm/board/sgiclarka/include/platform_def.h
plat/arm/css/sgm/include/sgm_base_platform_def.h

index eeb72de51ee885f5c79ce4100c59f4f6f119f4eb..ff75c6916442d6a02a3204ee3bf112da65d08f4e 100644 (file)
@@ -11,9 +11,6 @@
 #include <psci.h>
 #include <stdint.h>
 
-/* System power domain at level 2, as currently implemented by CSS platforms */
-#define CSS_SYSTEM_PWR_DMN_LVL         ARM_PWR_LVL2
-
 /* Macros to read the CSS power domain state */
 #define CSS_CORE_PWR_STATE(state)      (state)->pwr_domain_state[ARM_PWR_LVL0]
 #define CSS_CLUSTER_PWR_STATE(state)   (state)->pwr_domain_state[ARM_PWR_LVL1]
index 735e4a3369a5930c7fb391f3cc0975f5a1f9036f..0414f6cc107f84a531349cbd698400a4f18eb385 100644 (file)
 #define PLAT_ARM_PRIVATE_SDEI_EVENTS   ARM_SDEI_PRIVATE_EVENTS
 #define PLAT_ARM_SHARED_SDEI_EVENTS    ARM_SDEI_SHARED_EVENTS
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL         ARM_PWR_LVL2
+
 #endif /* PLATFORM_DEF_H */
index 3e48397810a4cf287278087068858d146244710a..fa639ca95a745e4b30b2b8e616dd3a9587e0e086 100644 (file)
@@ -32,6 +32,8 @@
                                                N1SDP_MAX_CPUS_PER_CLUSTER *    \
                                                N1SDP_MAX_PE_PER_CPU)
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL                 ARM_PWR_LVL2
 
 /*
  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
index c06a0a1fa8932dede1b340b92667aad26b851ee6..394a2e829145fc1e54f0741d7c605f3aa9523798 100644 (file)
@@ -20,4 +20,7 @@
 #define SGI575_DMC620_BASE0            UL(0x4e000000)
 #define SGI575_DMC620_BASE1            UL(0x4e100000)
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL         ARM_PWR_LVL2
+
 #endif /* PLATFORM_DEF_H */
index ba6d0434bb7eb1f63aaa7eb160521017d107a189..6de15c43271bce053e67d70239262b2c39ee708a 100644 (file)
@@ -20,4 +20,7 @@
 #define SGICLARKA_DMC620_BASE0         UL(0x4e000000)
 #define SGICLARKA_DMC620_BASE1         UL(0x4e100000)
 
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL         ARM_PWR_LVL2
+
 #endif /* PLATFORM_DEF_H */
index a9795a484ce78f3fa78e088f3dca586deaf13e2e..2178f069a5ea9983611663cb5af8564b6a741086 100644 (file)
  */
 #define PLAT_ARM_MEM_PROT_ADDR         (V2M_FLASH0_BASE + \
                                         V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/* System power domain level */
+#define CSS_SYSTEM_PWR_DMN_LVL         ARM_PWR_LVL2
+
 #endif /* SGM_BASE_PLATFORM_DEF_H */